ABSTRACT

Wavelet transforms have proven to be useful tool for several signal processing applications, including image and video compressions, image segmentation, speech synthesis and telecommunication. With the continuous increase in the use of internet and wireless devices, wavelet transform become more popular over traditional Fourier and cosine transforms in DSP applications especially for embedded multimedia applications. Designers are trying to develop more computation and energy-efficient VLSI architectures for discrete wavelet transform (DWT) so that it can be mapped into application specific DSP processors or into FPGA based reconfigurable coprocessors for embedded electronic devices. Several VLSI architectures have been proposed for computing 1-D and 2-D DWT which range from SIMD arrays to folded architectures such as systolic arrays and parallel filters. This paper proposes an efficient architecture for DWT computation based on systolic array model and its configuration as IP core in FPGA based reconfigurable coprocessors. The proposed architecture may be applicable for computation intensive DSP applications for mobile devices.