ABSTRACT

This paper presents the behavioral model of an Address Generation Unit (AGU) in a DSP Processor whose instructions are almost compatible with the Motorola DSP56002. The proposed AGU unit can handle 4 different types of arithmetic – linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles various means of calculating addresses as post/pre increment/decrement by a number. The novelty in this proposal is that it can address 2 different memories, where 2 new addresses are calculated concurrently. The central idea behind this design is address sequence generation by means of reverse carry addition, the use of modulo adder and offset adder. The designed AGU circuit generates the actual address as per the given set of inputs. Simulation results are compared with the theoretical data and found correct. The designed AGU may be implemented in a DSP Processor with optimized power and speed.