ABSTRACT

In this paper, low power multiplier design using complementary pass-transistor asynchronous adiabatic logic is investigated. Adiabatic circuits are very low power circuits compared with CMOS logic circuits, provided the Power Clock Generators consumes less power and mutilate all low power advantages from the adiabatic logic by consuming large portion of the total power in the clock generation circuitry [1, 2]. Also clock routing is major challenge in the adiabatic, because of routing-delay between the gates. To get out of the problems related to clock generation and synchronous clock routing, a new solution namely asynchronous adiabatic logic [5] is used. Here we have designed, simulated a multiplier with Complementary Pass- Transistor Asynchronous Adiabatic Logic (CPTAAL) which exhibits low power and reliable logical operations comprising the benefit of both asynchronous systems with adiabatic benefits. Compared with the conventional CMOS implementation, this design achieves energy savings from 50% to 74% for clock rates ranging from 100MHz to 300MHz.