ABSTRACT

Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power dissipation. Dynamic CMOS circuits, featuring a high speed operation are used in high performance VLSI designs. In this work, different types of AND gates with Conventional Body Bias & Forward Body Bias inverters are compared with their performances and the high performance circuit was specified. The different design styles are compared by performing detailed transistor-level simulation on bench mark circuits using CAD tools of DSCH3 and Microwind3 in sub-micron regime. The simulated results are compared in terms of power dissipation, propagation delay, PDP and area.