ABSTRACT

The carry propagation during the addition operation limits the speed of arithmetic operation. In Digital arithmetic, several approaches were proposed to provide the best implementation for addition operation of two operands with minimum carry propagation delay. A well-known property of Signed-Digit-Adder (SDA) is that the (ith) digit of the sum is exclusively dependant on the (ith) digit. In this paper, we propose an Efficient Hardware Design and Verification of Signed-Digit-Adder for two Signed-Digit Radix-4 Operands benefiting from the inherent parallelism of the SDA's operation and the use of basic structural logic circuits at the gate level. This new design will form an adder for two singed-operands of symmetric redundant number representation system with a fixed radix-4 system. Simulation results shown that the Proposed work enhance the critical path delay of the SDA-unit by 55%.