Energy Efficient Design of Logic Circuits Using Adiabatic Process

-In today’s electronic industry the Low power has emerged a principle theme. The most important features of modern electronic equipment is energy efficiency, it is designed using high speed and its portable applications. Power consuming can be reduced by adopting different style which is said to be excellent solution to low powerelectronic appliances. The adiabatic logic will be used as an efficient energytechnique for digital designs in this paper. The proposed system offers low power dissipation when compared to conventional CMOSlogic [1-6]. This paper provides full adder in various adiabatic logic styles and its results are compared to conventional CMOS logic. This simulation output specifiesas that proposed system is beneficial for various low power digital applications.


Fig1
. Charging and discharging of conventional type -CMOS logic.
Energy collected at the capacitor E(CL)= CL*VDD^2/2.Half of the supply energy will be dissipated in the PMOS [3].During VDD-0 no energy transfer takes place through PMOS but energy is transferred through NMOS. In conventional design 3typesof power dissipation dynamic switching, short circuit dissipation, leakage dissipation. Dynamic switching [9] is the most dominant type of switching.The switching powerdepends only on the supply voltage, the shifting frequency, the starting and ending voltages, and the corresponding capacitance of a switching terminal [10]. In order to reduce the power dissipation reduction of VDD supply voltage m oust be done or node capacitance CL must be reduced. Instead of varying these parameters adiabatic logic design is preferred over conventional CMOS logic design.

A.Conventional CMOS Design (Full Adder)
In this design PMOS pull up network as well as NMOS pull down network is used input source is given VDD supply.

A.Types o
Vari of logic c 1.

3.2-Phase Adiabatic Stratic Clock cmos Logic (2-PASCL) :
The Two Phase Adiabatic Static Clocked Logic (2-PASCL) uses two phase clocking split level sinusoidal power supply's it has both symmetrical and unsymmetrical power clocks where one clock is in phase while the other is out of phase [8]. The circuit has two diodes in its construction where one diode is placed between the output node and power clock, and another diode connected between one of the terminals of NMOS and power source. Both the MOSFET diodes are used to repeat charges from the output terminal and to increasing the discharging speed of input signal nodes. The circuit operation is divided into two phases "hold phase" and "evaluation phase". During the evaluation phase, the power clock swings up and power source swings down. During the hold phase, the power source swings up and power clock swings down.

IV. PROPOSED DESIGN OF FULL ADDER A.ECRL DESIGN (FULL ADDER)
It uses only two PMOS transistors with2 N-Blocks one with buffered input other with complementary input. Dual outputs are obtained in buffered as well as inverted output.It has 2 separate circuits for sum as well as carry.   Table 3. Power report of (ECRL sum) logic.

A.PFAL DESIGN (FULL ADDER)
In this circuit PMOS network is connected parallel to the n block inputs.It comprises of n block inputs as well as complementary inputs .Out puts are obtained in both buffered as well as complementary form. It has both sum as well as carry circuit.

B.2-PASCL DESIGN (FULL ADDER)
This design consist of two diodes in itsconstruction.One diode is placed between the output node and power clock. Another diode is connected between one terminals of NMOS and power source. This has a separate sum as well as carry.

4)
Min power 5.240466e-010 at time 1e-008.  Average power consumed -> 2.440594e-004 watts 3) Max power 1.001503e-003 at time 1.1e-008 4) Min power 2.694776e-010 at time 0  From this logic it is inferred that PFAL logic dissipates less power as compared to other types of logic. V. CONCLUSION Hence it is observed that, Adiabatic CMOS circuits can be efficiently used to implement a digital circuit design using gradually rising and falling power-clock. Retractile cascade power clocks or multiple phase power clocks with memory schemes can be used in large circuit design with low power consumption. The adiabatic circuit design can be further improved by introducing conventional power supply. Further to improve switching speed of adiabatic circuit as compared to CMOS logic we can design new adiabatic circuits with much better switching speed.