Feasibility of Successive Approximation Register ADC in Ultra Low Power Biomedical Applications

Analog-to-Digital Converter (ADC) is a critical block of the sensing unit of an implant and for measurements of various biophysiological signals, such as Electrocardiogram (ECG), Electroencephalogram (EEG) and Electromyogram (EMG) that covers the distinct portions of the frequency spectrum and signal bandwidths. ADC consumes about 30~35% of the total power of the device which is very high. Hence, for biomedical implants which require ultra low power consumption and low complexity to reduce the size and cost of the devices, there is a need of energy-efficient ADCs that conform to these restraints. This paper presents a study on the feasibility of ultra low power Successive Approximation Register (SAR) ADC in these biomedical applications. Various SAR ADC architectures proposed in the past decade to achieve ultra low power consumption have been investigated and their performances have been compared with respect to the parameters such as resolution, sampling frequency, signal–to-noise and distortion ratio, figure of merit among others. This paper also discusses the different switching schemes proposed to reduce the switching power consumed by the DAC. Finally, the future research scope and areas to further achieve ultra low power consumption without degrading the overall performance of the ADC has also been presented. Keyword-ADC, Biomedical Applications, SAR, Ultra Low Power Electronics

. General block diagram of a bioelectric signal acquisition system [3] It is observed from Table 1 that different neural signals are usually spread over a narrow range of amplitudes and frequencies ranging from few Hz to 200Hz and μV to mV except for spike signal which can have the maximum frequency of 7 kHz, whereas ECG is a very weak signal with an amplitude range of 1-5 mV at very low frequencies of 0.05-100 Hz [4,5]. Since these signals are low level hence they require low noise operation which makes it a difficult task to design a biomedical sensor interfaces for these biophysiological signals.
TABLE I Amplitude and frequency ranges of various electrical signals from the brain [4] Biosignal Type

Spike
Recording of signals generated from individual neurons by extracellular microelectrode inside cortex 500 µV 0.1 -7 kHz LFP Recording of signals generated from multiple nearby neurons by extracellular microelectrode inside cortex < 1 mV < 200 Hz ECoG Cerebral cortex activity monitoring and recording using disk electrodes placed on the exposed surface of the brain 0.01 -5 mV < 200 Hz EEG Recording of non-inactive electric activity from the brain 5 -300 µV < 100 Hz Hence to capture these signals accurately the acquisition system has to incorporate a low noise amplifier with desirable gain as shown in figure 1 along with a band-pass filter to lower the d.c. offset and noise of input signal and an ADC with resolution greater than or equal to 8 bits along with minimizing the power consumption to prolong the battery lifetime.
An ADC circuit that can acquire and isolate these neural and cardiac signals while maintaining ultra low power and low noise performance over all the ranges of operations offers obvious advantage over the one that is tailored to for a specific signal. It is desired to maintain low noise and ultra low power performance over all the ranges of operations. Various topologies of ADCs such as Sigma-Delta, Pipelined, Cyclic, etc. have been investigated over the years for Ultra Low Power operation in biomedical applications. However, one topology that has stood out of them for ULP applications is Successive Approximation Register (SAR) ADC due to its small active area and minimal requirement for active analog circuits. It is observed from fig. 2 that SAR topology delivers high performance on lower end applications such as biomedical, sensors etc. which operate at lower sampling rates from few kHz to few GHz. The reason behind its popularity in low speed applications are its ability to operate completely in dynamic manner which leads to almost zero static power consumption and the fact that CMOS technology is able to provide the switching speed required for sequential conversion of the analog signal.

II. SUCCESSIVE APPROXIMATION +REGISTER ADC
The function of sampling and holding an externally input analog signal is done by a Sample and Hold Amplifier (SHA) in a Successive Approximation Register (SAR) Analog-to-Digital Converter. This is shown in figure 3. Along with the SAR logic circuit, a comparator is also used for comparing a level of an analog signal corresponding to 'N' bits and generating a comparison signal according to the result as shown in figure 4. This is used for generation of digital signal from sequentially generating a digital signal from a Most Significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal and a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output/code register for holding the sequentially generated digital signal from the MSB to the LSB to generate an N-bit digital signal, wherein, upon externally receiving a START signal, the SAR logic circuit generates a digital signal of a MSB having a 1-bit phase delay compared to the START signal [7] [8]. A single-chip highly integrated low power mixed-signal IC has been proposed for Implantable Pacemaker Application in [9], to sense the heart rate and deliver electrical stimulation, instead of using several analog ICs. The primary goal is focused around low-power analog and digital design techniques to prolong single battery operations. An 8-bit SAR-ADC has been used in the sensing system of the proposed IC to digitize the input ECG signal. In this ADC, power is mainly consumed by Sample and Hold Amplifier (SHA), DAC and comparator. To minimize this power, binary weighted capacitor array for DAC has been utilized along with integrated single op-amp which consists of three class-AB amplifiers or inverters that have been used for both S/H and comparator. At a supply voltage of 2V the current consumption of the ADC is around 150 nA and the power dissipated by the entire system is 8 μW when fabricated in a 0.5 μm two-poly three-metal multi-Vt process.
Binary search algorithm architecture has been proposed in a traditional SAR ADC to replace its conventional DAC to significantly reduce the system area and power consumption for biomedical instruments in [10]. It has variable resolution and eliminates the need for resistors and a high current reference source. A digital flip-flop is employed as storage device for the output of the comparator and the amount of digital logic involved is minimal which results in the elimination of cross-talk between analog and digital components and reduces the complexity of the layout process. With a conventional battery supply of 2V, the power consumed by the proposed ADC is 22.2 μW with a very high resolution of 16 bits, which is almost 52% lower than conventional SAR ADC power consumption. Hence it is a possible solution in applications where size and low power operations are necessary such as in portable biomedical devices.
The proposed design in [11] is a biomedical signal acquisition IC which consists of low noise instrumentation amplifier with DC rejection, an 11 bit SAR ADC, other auxiliary circuits and still consumes only 2.3 microwatt of power at supply voltage of 1V. The ADC proposed for the IC does not have a dedicated S/H in order to conserve power. It however consists of the output stage of low noise OTA as a pseudo S/H circuit and it also uses a dynamic comparator with negligible power consumption when inactive.
One of the techniques used to save power is to reduce the consumption at charging and discharging of capacitor array. Using the binary search based operation, the SAR architecture has been modified in terms of power in [12]. A switching technique has been proposed for saving energy in this paper, which is combined with capacitor splitting technique and splits MSB/2 capacitor into the binary weighted sub capacitor array. This technique lowers the power consumption during the up paths of each switching phase. At the supply voltage of around 1V, the power dissipation using this technique has been reduced to 7.75 µW, i.e. around 56% saving in energy in comparison to conventional ADCs. Whereas the switching energy required in the conventional ADCs increase with the length of output code, using this technique however the switching energy remains constant.
An SAR ADC which employs splitting comparator and energy saving capacitor array, suitable for wireless sensor networks and biomedical applications at low power consumption has been proposed in [13]. The coarse and fine comparison in the splitting comparator is done by two comparison paths consisting of detector and two topology comparators. This is shown in Figure 5. This comparator acts like a hysteresis comparator to select the adjustable window size path. A fully dynamic regenerative latch is used in the coarse comparator architecture whereas fine comparator is an output offset storage comparator. Using this proposed architecture 42 µW of power is dissipated at the supply voltage of 1V. Fig. 5. Energy saving capacitor array SAR ADC architecture [13] A system on chip has been proposed for the feature detection and to detect the onset of seizures of EEG channel and hence convert these analog EEG signals to digital domain in [14]. For feature vector streaming, the Instrumentation Amplifier (I-amp), which amplifies the 10-50 µV EEG Signal from the passive scalp electrodes, an ADC, a processor for feature extraction and a low power parallel-serial interface, has been integrated into a single central device. It further employs a control gate to ensure that static bias remains ON for the period of conversion. A 12 bit ADC used in this architecture uses a 6-bit main ADC and a 6-bit sub ADC Architecture and works at the sampling rate of 100 kS/s to achieve the power consumption of 25 µW at 1V supply.
Addressing the low power consumption requirement in the growing area of portable bio-potential acquisition systems, an ultra low power, low noise and small chip area SAR ADC has been proposed in [15]. Compared to the conventional SAR, the proposed SAR has additional auto-zeroed preamplifier to suppress offset voltage, is placed before the latch which is offset calibrated by adding unbalanced capacitors to conserve power. Also to address the problem of low kick-back noise, a low kick-back noise latch is proposed in this paper which has four additional transistors compared to the conventional latch and hence there are very less glitches in the output. The chip was fabricated in 0.18 μm CMOS process and the power consumed by this design is only 455 nW for a supply voltage of 1.8V and a resolution of 12 bits. Although this ADC was designed for biopotential acquisition system, it can also be used in other high resolution and low speed applications with a very low power consumption requirement.
The authors in [5] have proposed system architecture of current mode ADC with an aim to achieve ultra low power consumption and small die area for pacemakers which detects the IECG signals. Current mode SAR ADC has been has been used because it does not use operational amplifiers and its power consumption is directly proportional to the full scale current input, as shown in figure 6. To achieve small area, unary-weighted current source array has been used as DAC instead of using capacitors. The 8-bit design is simulated using IBM 0.13 μm CMOS technology parameters and the temperature is set to 37 ˚C as that of human body and. The total power consumed by the proposed 8-bit current mode SAR ADC is 255 nW, designed using 0.13 μm CMOS technology and a supply voltage of 1V and simulated at 37 ˚C. For IECG applications this power consumption is almost 50% of the lowest reported ADC for similar design specifications. [16] proposes a leakage reduced CMOS switch for 10 bit SAR ADC working at a sampling rate of 1 kS/s taking into account its various design constraints. The emphasis is on sampling circuit which during the operation of ADC introduces various linear and non-linear effects and hence degrades the accuracy of the ADC. It is observed that high VDD is favorable but it increases power dissipation and decrease of sampling frequency provides large margin for jitter reduction and bandwidth design but it introduces reverse voltage droop. The total power dissipation of this SAR ADC is 64 nW at a supply voltage of 1V of which 34 nW (53%) is consumed by SAR logic and 28 nW (44%) by capacitor array.
A highly integrated analog front-end (AFE) IC design for monitoring brain-heart biosignals such as Diffuse Optical Tomography (DOT), Electrocardiography (ECG) and Electroencephalography (EEG) has been presented in [17]. It features a fully integrated eight-channel design for low power operation in which each channel shares a common ADC which is employed in conjunction with an analog multiplier to select the particular bioelectric signal for digitization. The IC employs a 10-bit SAR ADC as it is advantageous in terms of area and power. To improve the SNR of the ADC, a parallel configuration based comparator has been used which also increases the common mode range whereas, a split capacitor based DAC has been proposed which is deprived of any capacitor scaling and thus achieves lower power consumption. The total power consumed by the IC is 506.36 μW of which only 8.27 μW is consumed by the proposed ADC when operated at a sampling frequency of 100 kS/s and supply voltage of 1.8 V. Hence this IC design achieves the goal of low power operations while maintaining low noise.
In [18], an SAR ADC that utilizes a common mode resetting tri-level switching scheme and a time domain comparator with redundant algorithm is presented for applications like wearable sensor nodes and implantable medical devices powered by batteries or wireless charging, as shown in figure 7. The requirement of low power consumption has been achieved by reducing the static and switching power consumed by the ADC, where the switching activity and power is reduced by the proposed common mode resetting tri-level switching scheme and the time domain comparator has been used due to its low voltage operation ability and zero static power consumption. The SAR ADC consumes only 400 nW power at a 1V supply voltage of which 52% of the power is consumed by the comparator, 23% by SAR logic, 23% by the capacitor array and rest by the clock buffer. Fig. 7. Tri-level switching based SAR ADC [18] [15] With the focus to reduce the battery lifetime, a power efficient Successive Approximation technique based ADC has been used to digitize the ECG signals acquired by the wavelet based ECG detector, for monitoring the heart-beat rate and its rhythm in a low power and energy efficient Implantable Pacemaker Integrated Circuit (IPIC) proposed in [19]. This SAR-ADC achieves lower power consumption by using voltage scaling and clock gating technique. Due to low sampling rate of IPIC and relatively faster conversion speed of the ADC, large portion of ADC is inactive most of the time, hence switch-attached ON/OFF time controlled comparator and time interleaved passive S/H with no static current has been implemented which further reduces the static power consumption of the SAR-ADC. The proposed test chip when fabricated at 0.35 μm CMOS technology achieves a low power consumption of 19.02 μW with a supply voltage of 3V of which 5.4 μW (~29%) is consumed by the SAR-ADC.
With the goal to reduce the power consumption and reduce noise to improve the signal-to-noise ratio, this paper presents a new of architecture of SAR ADC in [3]. The accuracy is determined by the DAC which is its core component, hence an energy efficient binary capacitor array has been used in this design and the capacitance is almost halved compared to the conventional DAC. Dynamic latched comparator has been designed along with synchronous SAR logic to save energy and a dynamic amplifier has been inserted between the DAC to reduce the kick-back noise and accelerate the speed. Generally, for EEG acquisition system an ADC with 10-bit resolution is preferred to achieve better accuracy. For a supply voltage of 1.2V the power consumption is 120 nW and 2.96 μW for 1 kS/s and 30 kS/s sampling frequency respectively. For a supply voltage of 1.8 V the power consumption is 270 nW and 6.32 μW for 1 kS/s and 30 kS/s sampling frequency respectively. Hence the proposed 10-bit SAR ADC can be used for biomedical devices which require ultra low power consumption and low speed.
An SAR ADC has been proposed in [20] for biomedical signals which are particularly very low frequency signals in nature. Power efficiency in SAR ADC has been achieved by reducing the total capacitance of DAC and the speed of its operation whereas the S/H uses a capacitor and an analog switch to connect or isolate from the input. To reduce the area, the 10-bit DAC has been sub-divided into two 5-bit DACs and is implanted using split-array capacitive charge redistribution architecture. For a supply voltage of 1.8V, the power dissipated by the proposed ADC is only 1.502 μW with a higher resolution compared to other ADCs for the same design specifications.
An ASIC for single chamber leadless pacemaker at ultra-low power (sub µW) consumption centered at high quality ECG signal acquisition and classification has been proposed to readout and extract the information from the ECG signal using QRS complex extractor in [21]. In order to reduce the consumption of power, feature extraction is performed in analog domain followed by digitization where an ADC converts both time domain ECG signal (ECGout) and feature extracted signal (FEout) before feeding the signals to DSP. This architecture contains a 9-bit capacitor array, which is used as sampling capacitor, as well as feedback DAC. With the supply voltage varying from 1.3-1.8 V, the current consumptions of channels is 350 nA (44%), that of ADC is 110 nA (17%) and other supporting circuits consume 220 nA (32%), thus the total current consumed is 680 nA.

IV. DISCUSSIONS
The operation at a very low supply voltage (1-1.5V) with ultra low power consumption for long battery lifetime are some constraints possessed by the wearable medical devices that are desirable to operate under single micro battery. This arises the need of extremely low input referred noise to pick up these very weak signals. The SAR designs are gaining popularity for ultra low power applications due to the aggressive scaling of unit capacitance, scaling of digital logic with low power leakage and the ability of the comparator to operate in subthreshold region. Some of the recently proposed SAR ADCs for different biomedical applications have been studied and surveyed and the feasibility analysis of these ADCs is done with respect to their performance parameters such as resolution, sampling frequency, SNDR, SNFR, power consumption, effective number of bits (ENOB), integral and differential non-linearity along with the figure of merit (FOM) and can be summarized by Table 2. It is observed that power as low as 38 nW has been achieved by authors in [22] for a 10-bit SAR ADC for use in biomedical implants. The performance of these ADCs indicates that for a resolution of 8-12 bits, SAR topology is feasible enough to achieve ultra low power operation while maintaining the other desired performance parameters. As the resolution is increased beyond 12 bits the power consumption of SAR increases drastically and hence requires new design techniques to reduce the power at higher resolution.

V. CONCLUSION
It is concluded that the input range of all the biophysiological signals lie within the range of 0-50 mV with frequency ranging from near DC to 200 Hz except for the neural spike signals which lies in the range of 0.1-7 kHz. In context to the micro-power medical devices, not speed but ultra low power conversion of these low amplitude and frequency biophysiological signals is paramount. This in conjunction with the accuracy required in the conversion accuracy of these biophysiological signals makes the design and development of ADCs with these specifications a major challenge in order to increase the efficiency of the battery. The main focus of research heretofore has been on medium resolution (8-12 bits), moderate and particularly high speed applications. Technologies such as optimization of the control logic, new structures for DAC, new switching schemes and designing of comparator have been applied to these SAR ADCs but they remain unexplored in biomedical realm in terms of efficient design methodologies and circuit techniques. Another research aspect that is yet to be explored is the performance degradation of the ultra low power ADCs.