Design of Energy Efficient Dual Spacer Delay Insensitive Ripple Carry Adder with better Slew Rate

:- The main goal of this paper is to provide the low power solutions for Very Large Scale Integration (VLSI). Design of low power and area efficient logic systems forms an integral part in the field of VLSI design. The addition is the most fundamental part in the arithmetic operations. To perform fast arithmetic operation, Ripple carry adder (RCA) is one of the fastest adder used in many data processing applications. Various Delay Insensitive techniques are available for designing low power applications. In this paper, the features of Multi-threshold Null Convention Logic (MTNCL) are discussed and we implement Ripple Carry Adder using proposed Multi-threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD 3 L). Proposed and existing techniques are compared in terms of various performance metrics like power, delay, energy and slew rate.


B. Basic Full adder
A full adder is basically used for adding and consist three inputs (A n , B n , C n-1 ) where A n and B n are the n th order bits of the numbers A and B respectively and Cn-1(C in ) is the carry generated from the addition of (n-1) th order bits and provides Sum (S), Carry Out (C out ) as shown in figure.2. The table.2 represents the truth table for full adder [6,7].   This paper is organized as follows: In section 2, implementation of Half adder and Full adder in asynchronous techniques. Section 3, explains about ripple carry adder and design in asynchronous techniques. Section 4 deals with a few applications of design and results are evaluated in section 5 and section 6 concludes.

II. DESIGN OF ASYNCHRONOUS CIRCUITS
The Asynchronous (self-timed circuits) techniques are Multi-threshold Null Convnetion Logic (MTNCL) and proposed Multi-threshold Dual rail Dual spacer Delay insensitive Logic (MTD 3 L) [9]. The Half adder and Full adder were implemented with some threshold gates of 27 Fundamental threshold gates. In this self-timed circuits, each single bit as a dual rail. Consider Half adder and full ADDER implementation in clockless circuits [5,13].   represents the truth table of full adder in dual rail [8,10]. Each single input and output acts as a dual rail (A 0 , A 1 , B 0 , B 1 , C 0 , C 1 , S 0 , S 1 , Cout 0 , Cout 1 ). To design the full adder in self-timed circuit, two different threshold gates are required which are TH 23 , TH 34W2 out of 27 fundamental gates.
The basic Null Convention Logic consists of SET, RESET blocks for circuit operation and Hold 0 , Hold 1 blocks for state holding capacity [14]. While applying the multi-threshold to NCL logic, the circuit area and power consumption will be reduced i.e., transistor count is decreased. For MTNCL, only Hold 0 and SET blocks [15] are required and additionally few high threshold voltage transistors (V th ) are used to reduce the leakage problem as shown in figure.5 [19].

III. PROPOSED MULTI-THRESHOLD DUAL-SPACER DUAL-RAIL DELAY-INSENSITIVE LOGIC (MTD 3 L) -RIPPLE CARRY ADDER
The block diagram of MTD 3 L is similar to MTNCL logic, but two sleep signals (sleep0, Sleep1) are required in this logic as shown in figure.6 [14]. The circuit will operate with respect to the input signal, when two sleep signals are transitioned to 0 as shown in table.5. If sleep 1 signal is asserted, then all one spacer is obtained as the output. If sleep0 is asserted, then all zero spacer is obtained as the output [15,20].  Ripple carry adder is constructed by cascading full adder block in the series or it can be constructed by merging half adder and full adder blocks. This paper deals with the combination of full adder and half adder block in series for 8-bit ripple carry adder circuit with multiple full adders and half adder can be used to add N numbers and each full adder inputs a C in , which is the C out of the previous full adder. Such kind of adder is known as Ripple carry adder, since each carry bit ripples to the next full adder as shown in figure.7. So ripple carry adder in digital electronics is that circuit which produces the arithmetic sum of two binary numbers [12]. The input bits of 'X' are added to the input bits of 'Y', respectfully of their binary position. Each bit addition creates a sum and a carry out. The carry out is then transmitted to the carry in of the next higher order bits. The final result creates a sum of N bits plus a carry out [16,18].
The 8-bit ripple carry adder was implemented in two asynchronous circuits (MTNCL and MTD 3 L logics) as shown in figure 8 and 9.
In many computers and other kind of processors, adders are not only used in the arithmetic logic unit, but also in other parts of the processor, where they are used to calculate addresses, table indices and similar applications [11]. Some other applications of adders are in Multiply-Accumulate (MAC) structures, Arithmetic Half adder

Full adder
Full adder Logic Unit (ALU). Adders are also used in multipliers, in high speed integrated circuits and Digital signal processing (DSP) to execute various algorithms like FFT, IIR and FIR [17].

IV. SIMULATION RESULTS
This work has been developed with Mentor Graphics tools with 130nm technology. The simulation results (output waveforms of a single rail) of the ripple carry adder using the two asynchronous techniques (MTNCL and MTD 3 L) as shown in figure 10 and 11. Table.6 shows the comparison of two asynchronous techniques (MTNCL, MTD 3 L). The parameters which compared on power dissipation, delay, energy and slew rate.

A. Power Dissipation
Power dissipation is one of the main criteria which, considered in the VLSI design. As power dissipation (heat) is reduced, the output waveforms will obtained accurately without any glitches. Average dissipated power for ripple carry adder in two self-timed logics are tabulated in 6.
Pavg = Pstatic + Pdynamic Where Pavg is the total average power, Pstatic is the static power dissipation,Pdynamic is the dynamic power dissipation of the circuit.

B. Propagation delay
Propagation delay or Gate delay is the time required for a digital signal to transit from the input voltage of a logic gate to the output voltage. Delay must be reduced to obtain the circuit performance accurately (high speed) and glitches will extract. It is given by Power Delay Product (PDP) is the measure of energy and is defined by the product of power and delay to measure the circuit performance. It is measured in Joule. The advantage of increasing the energy is short circuit dissipation (leakages) is minimized. It is given by PDP = P Power x T delay Where P is the average power and T is the propagation delay or gate delay.

D. Slew Rate
Slew rate is defined as the rate of change of voltage per unit time. The unit of measurement is Volts/Sec.

SR 2πfVpk
Where f is the frequency ( and Vpk is the peak amplitude of the waveform. The high slew rate gives quicker response, i.e., changes the state of the output with respect to the input, especially at high frequencies as shown in waveforms and tabular form 6.

V. CONCLUSION & FUTURE SCOPE
The ripple carry adder is designed using two CMOS asynchronous techniques. Proposed MTD 3 L gives better performance interms of delay, % of energy savings and slew rate. With proposed method we achieved 97.5% energy savings. The ripple carry adder design may further optimized in terms of all these performance metrics by using Return To One Protocol and leakage reduction technique like LECTOR algorithm.