Single Active Element Based Three input Single output Trans-admittance mode Biquad Universal Filter

In this paper, a new three input single output trans-admittance mode biquad universal filter is proposed, which employs only single active element, namely modified differential voltage current conveyor trans-conductance amplifier (MDVCCTA) and four passive elements in the form of two capacitors and two resistors. Two of the passive elements used in the proposed structure (one resistor and one capacitor) are permanently grounded. The proposed circuit is capable of realizing trans-admittancemode low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) filtering responses. The two filter parameters such as quality factor and bandwidth are electronically tunable without effecting the pole frequency. In addition, the proposed filter circuit also enjoys the low active and passive sensitivities. PSPICE simulation results using 0.35um CMOS technology are shown to prove the performances of the proposed circuit. KeywordTrans-admittance-mode, analog signal processing, filter, biquad, DVCCTA.


II. DESCRIPTION OF MDVCCTA
Recently DVCCTA have been extensively used as current-mode active element in designing of analog circuits [7], [25]- [26]. Modified DVCCTA (MDVCCTA) is the modified version of recently proposed DVCCTA and offers the additional electronic tunability option over conventional DVCCTA. The schematic symbol of MDVCCTA is shown in Fig. 1. The input port X is a low impedance port and transfers the copy of its current (I X ) to two auxiliary ports Z 1 and Z 2 . The input ports Y 1 and Y 2 are input high impedance ports and ideally current in these ports is equal to zero. The voltages across auxiliary ports at Z 1 and Z 2 are transferred to currents I O1 and I O2 across high impedance output ports O 1 and O 2 , respectively, by trans-conductance parameter g m1 and g m2 , respectively. Both trans-conductance parameters g m1 and g m2 are electronically controlled by biasing currents I S1 and I S2 of the MDVCCTA. The ideal equations governing relationship of voltages and currents between various input-output ports of MDVCCTA as shown in Fig. 1 can be described as The internal circuit of MDVCCTA, implemented with CMOS technology is shown in Fig. 2. For the CMOS realization, the value of g m1 and g m2 as a function of biasing currents I S1 and I S2 , respectively, can be derived as following equations. n S1 g = β I and m2 n S2 Here, µ is the electron mobility, C OX is the gate oxide capacitance per unit area and W/L is aspect ratio of NMOS transistors M 17 -M 18 and M 23 -M 24 .

III. PROPOSED TRANS-ADMITTANCE MODE BIQUAD FILTER
The proposed trans-admittance biquad filter is shown in Fig.3. It consists of only single MDVCCTA, two capacitors (C 1 and C 2 ) and two resistors (R 1 and R 2 ) with one capacitor (C 1 ) and one resistor (R 2 ) are being permanently grounded. By applying V 1 , V 2 , and V 3 as voltage input signals to the appropriate positions in the circuit as shown in Fig. 3 and re-analysing the circuit, the following expression for the output current I OUT can be obtained.
It is evident from above equations that the following trans-admittance-mode filtering responses can be obtained at I OUT by the appropriate selection of V 1 , V 2 and V 3 .

v.
AP filtering response when V 1 = V 3 =1, V 2 = 0 and g m1 = g m2 . Thus, the proposed circuit can realize all five filtering responses in trans-admittance-mode without requiring any inverted and/or scaled type voltage input signal(s). However, LP filtering and AP filtering responses require simple matching condition which can be justified in light of single active element used in the design of proposed biquad filter.
From D(s) described in equation (6), the expression of filter parameters such as pole frequency (ω 0 ), quality factor (Q) and bandwidth (BW) can be derived as It can be noted from (9)-(11) that the Q and BW can be electronically tunable without effecting ω 0 through single biasing current I S2 only.

IV. NON IDEAL BEHAVIOUR AND SENSITIVITY ANALYSIS
In this section, the effect of non ideal errors on the performance of the proposed filter circuit of Fig. 3, which may occurred due to mismatching of the various MOS transistors used in CMOS implementation of MDVCCTA, is considered first.
Taking these non-ideal errors into consideration, the voltage-current port relationship of MDVCCTA will be modified as described below -O1 1 m1 Z1 Where α 1 and α 2 are the current tracking errors from X to Z 1 and Z 2 , respectively. The β 1 and β 2 are the voltage tracking errors from Y 1 to X and Y 2 to X, respectively. The γ 1 and γ 2 are the trans-admittance gain tracking errors from Z 1 to O 1 and Z 2 to O 2 , respectively, which may be deviated from unity. Taking above nonidealities into consideration, if we re-analysed the proposed circuit of Fig. 3, the following output equations for the I OUT can be obtained.
The filters parameters of the circuit after considering tracking errors at various ports will be changed to It is clear from (19)- (20) that ω 0 and Q of the proposed filter of Fig. 3 will be deviated from the ideal case, due to the appearance of non-idealties. However, these deviations are very slight and can be neglected because non ideal parameters α 1 , α 2 , β 1 , β 2 , γ 1 and γ 2 can be found closed to unity at working frequency.
The sensitivities of the proposed circuit's pole frequency and quality factor with respect to various non ideal errors, active and passive components are determined as Evaluation of circuit in (21)- (22) for sensitivity shows that ω 0 and Q are less sensitive to non ideal errors, active and passive components and for them sensitivity value is less than or equal to unity in magnitude.

V. SIMULATION RESULTS
To verify the theoretical analysis of the proposed filter done in section II, PSPICE simulation on ORCAD tool was carried out. For this purpose, the circuit was designed by selecting the value of various active and passive elements as V DD = -V SS =1.85V, V BB =−0.85V, I S1 =I S2 =110µA, C 1 = C 2 =80pF, R 1 =R 2 =2KΩ and simulated was performed based on CMOS structure of MDVCCTA as shown in Fig. 2, with transistor model of 0.35µm MOSFET from TSMC. Aspect ratio of each MOS transistors of MDVCCTA used for simulation is given in Table 1. Fig. 4 and Fig. 5 shows the simulation results in term of magnitude and phase response of LP, BP, HP, BR and AP for the proposed trans-admittance-mode filter of Fig. 3. From the simulation results shown in Fig. 4 and Fig. 5, the pole frequency was obtained as 1.0965 MHz which is very much closed to designed pole frequency of 1.07 MHz. The power dissipation of the proposed circuit is 2.65 mW. In order to show the electronic tuning feature of Q independent of pole frequency for the proposed filter, the circuit was further simulated to obtain various BP responses at different value of I S2 and corresponding simulation results was shown in Fig. 6. From the Fig. 6, Q value was found (at constant pole frequency of 1.0965 MHz.) as 2.1, 1.08, 0.768 and 0.56, respectively, at different values of I S2 = 20µA, 80µA, 160µA and 300µA, respectively, which proves the electronic tunable capability of the proposed circuit.
To examine the total harmonic distortion (THD) produce by the circuit, the circuit was again simulated for THD analysis at HP, by applying sinusoidal input voltage of varying amplitude and constant frequency. The THD values at frequency of 10 MHz are shown in Fig. 7 which clearly shows that for the input voltage signal having amplitude less than 160 mV, the THD remains in acceptable limits i.e. 3%. Lastly, the time domain behavior of HP response with respect to sinusoidal input voltage is shown in Fig. 8. It is clear from the simulations that 100 mV peak-to-peak sinusoidal input voltages are possible without significant distortions.

VI. CONCLUSION
A new three input single output trans-admittance mode biquad universal filter based on only single active element namely MDVCCTA is proposed in this work. It also uses two capacitors and two resistors as passive element with two of the passive elements (one capacitor and one resistor) are permanently grounded. In addition, the proposed circuit offers the following attractive features.
i. Capable of realizing LP, BP, HP, BR, AP filtering responses in trans-admittance-mode.
ii. The circuit is canonical by the way of using only two capacitors.
iii. The circuit does not require any scaled or inverted type voltage signal to realize any filtering response which makes the circuit simpler. iv. The circuit provide the feature of electronic control of Q and BW independent of ω 0 through single biasing current and hence suited for practical applications. v. Active and passive components sensitivity is low. vi. Minimum number of active element. vii. Low power consumptions.