International Journal of Engineering and Technology

One of the nonlinear components in PLL is Phase Frequency Detector (PFD),the purpose is to compare two input frequencies in terms of their phase and frequency. In this process jitter will be introduced to the PLL system by PFD. proposed PFD is the preferred approach for detecting weak signals as from a deep space profile. The increase of MOS devices on a single chip will consume more power. Various applications of the PLL such as wireless communication systems, digital circuits, and receivers, targets optimum PFD Design. Optimized PFD reduces jitter effect on PLL and enhances the performance of PLL by increasing the locking range, reducing the phase error variance, reducing the acquisition time and reducing the power consumption. The power consumption in the design of PFD is dependent on CMOS logic of the gates In this paper we propose CMOS PFD, where the performance of the result will be analyzed by using Tanner EDA Tool by considering 45nm technology.