International Journal of Engineering and Technology

This study presents the design of low power 9T SRAM cell using dynamic domino logic to achieve low power dissipation. The internal structure of the proposed 9T SRAM has cross coupled dynamic inverters which periodically updates the internal node voltage levels which, increase the read and write stability of the circuit. The SRAM design also has charge keeper transistor which resolves the problems in charge leakage so that the node voltages are not affected. The study investigates the impact of read/write delay, power dissipation, read stability, write-ability, and compares the results with that of standard 6T, 9T and 10T SRAM cell. The comparative study is based on Monte Carlo simulation to analyse the power improvements with its counterpart. The simulation results reveals appreciable improvement in read and write delay of about 54% with 67% of power consumption when compared to the existing 6T, 9T and 10T SRAM cell.