International Journal of Engineering and Technology

The FFT(Fast Fourier Transform) processing is one of the key procedure in the popular orthogonal frequency division multiplexing(OFDM) based communication system such as Digital Audio Broadcasting(DAB),Digital Video Broadcasting Terrestrial(DVB-T),Asymmetric Digital Subscriber Loop(ADSL) etc.These application domain require performing FFT in various size from 64 to 8192 point. Implementing each FFT on a dedicated IP presents a great overhead in silicon area of the chip. By supporting the different sizes of FFT for new wireless telecommunication standard may increase the time to market it. This consideration make FFT ideal candidate for reconfigurable implementation. Efficient implementation of the FFT processor with small area, low power and speed is very important. This survey paper aims at a study on efficient algorithm and architecture for reconfigurable FFT design and observes common traits of the good contribution.